Embodiments of the invention relate generally to semiconductor device packages or electronics packages and, more particularly, to a power electronics package that includes an interconnect structure formed of a glass dielectric material.
Power semiconductor devices are semiconductor devices used as switches or rectifiers in power electronic circuits, such as switched mode power supplies, for example. Many power semiconductor devices are used in high voltage power applications and are designed to carry a large amount of current and support a large voltage.
In use, power semiconductor devices are typically mounted to an external circuit by way of a packaging structure, with the packaging structure providing an electrical connection to the external circuit and also providing a way to remove the heat generated by the devices and protect the devices from the external environment. Power semiconductor devices are provided with a number of input/output (I/O) interconnections to electrically connect both sides of a respective semiconductor device to an external circuit. These I/O connections may be provided in the form of solder balls, plated bumps, or wirebond connections. In the case of wirebond packaging, wirebonds are provided that connect bond pads or contact pads provided on the power semiconductor device to a corresponding pad or conductive element at the next level of packaging, which may be a circuit board or leadframe. Most existing power device packaging structures use a combination of wirebonds and a substrate (e.g., a direct bonded copper (DBC) substrate) to provide I/O interconnections to both sides of a respective semiconductor device.
As semiconductor device packages have become increasingly smaller and yield better operating performance, packaging technology has correspondingly evolved from leaded packages to planar build-up packages that incorporate buried or embedded semiconductor devices. The general structure of a prior art planar packaging structure 10 incorporating an embedded power device is shown in FIG. 1. The standard manufacturing process for the POL structure 10 typically begins with placement of one or more power semiconductor devices 12 onto a dielectric layer 14 by way of an adhesive 16 that is applied to dielectric layer using a spin coating technique. POL structure 10 may also include one or more additional die packages, packaged controllers, or other electrical components such as inductors or passive components 18. Dielectric layer 14 is a polyimide or other organic material, such as Kapton for example, which has a coefficient of thermal expansion of approximately 20 ppm/° C. Dielectric layer 14 is provided as a planar prefabricated film or lamination or is formed as a planar layer atop a frame structure (not shown).
Metal interconnects 20 (e.g., copper interconnects) are then electroplated onto dielectric layer 14 to form a direct metallic connection to the power semiconductor devices 12. The metal interconnects 20 may be in the form of a low profile (e.g., less than 200 micrometers thick), planar interconnect structure that provides for formation of an input/output (I/O) system 22 to and from the power semiconductor devices 12.
POL structure 10 also includes a direct bond copper (DBC) substrate 24, which is typically formed from a non-organic ceramic substrate 26 such as, for example, alumina, with upper and lower sheets of copper 28, 30 bonded to both sides thereof via a direct bond copper interface or braze layer 32. The upper copper sheet 28 of DBC substrate 24 is patterned to form a number of conductive contact areas before DBC substrate 24 is attached to semiconductor devices 12. An electrically conductive shim 34 is provided to electrically couple a portion of metal interconnects 20 to DBC substrate 24.
During the fabrication process of POL structure 10, solder 36 is applied to the surfaces of semiconductor devices 12 and shim 34. DBC substrate 24 is then lowered onto solder 36 to align the patterned portions of lower copper sheet 30 with solder 36. After DBC substrate 24 is coupled to semiconductor devices 12 and shim 34, an underfill technique is used to apply a polymeric dielectric material 38 in the space between adhesive layer 16 and DBC substrate 24. While polymeric dielectric material 38 provides some environmental protection for semicondcutor devices 12, the semiconductor devices are not hermetically sealed due to the inherent characteristic of the polymeric material 38 that allows moisture and other gases to diffuse through it.
Advancements in semiconductor chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization, and higher reliability. Such advancements have led to the development of new semiconductor technologies such as, for example, silicon carbide (SiC) power devices. These new power devices may be operated to switch at high frequencies and at high voltages. However, these devices also operate at elevated temperatures as compared to prior art devices, i.e., at temperatures above 150° C., with temperatures typically in the range of 150 to 250° C. but sometimes exceeding 300° C.
As explained with respect to FIG. 1, existing planar packaging technologies use polyimide and other organic materials for the various dielectric and encapsulating layers within the package structure. While these materials may provide for a planar package structure, polyimide and other organic materials are limited in temperature and reliability at elevated temperatures, as these materials have an upper temperature limit in the range of 150 to 175 degrees Celsius. Ceramic materials such as alumina may also be incorporated into planar packaging structures. However, the high cost and brittle nature of these materials severely limit their capabilities.
To fully utilize the capabilities of these new semiconductor technologies, it would be desirable to provide a new planar packaging technology that maintains reliability at the elevated operating temperatures, frequencies, and voltages of SiC and other high temperature power devices. It would further be desirable for such a packaging technology to hermetically seal the power devices and simplify the current manufacturing process.